1. Field of the Invention
This invention relates generally to the nondestructive testing of integrated circuits (ICs) and more specifically to a probe testing system including a compliancy system capable of reliably cushioning the contact force between the probes and the device under test (DUT).
2. Description of the Prior Art
Integrated circuits are manufactured by forming multiple layers of semiconductor circuits generally with repeated and fixed patterns to develop a plurality of "chips" on a thin planar substrate, i.e., a wafer. The wafers are then cut into individual chips for further processing and packaging. Individual chips, however, must first be inspected and tested to assure the quality and the reliability of the final products made from these semiconductor chips.
The testing operation is performed at a wafer level before the wafers are sawn apart into individual chips. The testing system typically comprises a test controller, which executes and controls the test programs; a wafer dispensing system, which mechanically handles and positions the wafers for testing; and a probe card, which maintains an accurate mechanical contact with the device under test (DUT) and provides an electrical interface between the test controller and the DUT. The probe card includes a printed circuit board known as the `performance board`. A performance board may be designed for individual ICs or IC families. The probe card also has a plurality of test probes which are accurately positioned to coincide with the input/output (I/O) pads of the device under test (DUT).
Under control of the test controller, a set of testing signals including of specific combinations of voltages and currents are generated and transmitted to the DUT via the performance board and the test probes. The output of the chips in response to the test signals are detected and transmitted by the probes to the test controller via the performance board. The voltage, current or frequency responses from the DUT are analyzed and compared with a set of predetermined allowable ranges. Chips which fail to meet the testing criteria are identified and rejected and the remainder of the tested chips are accepted for further process.
A conventional type of wafer probe card consists of a set of fine styluses or probes mounted on the performance board. The probes are arranged so that their tips form a pattern identical to that of the DUT's contact pads. The other ends of the probes are soldered to the traces of the printed circuits on the performance board for further connection to the test controller. The wafer dispensing system brings the wafer to be tested to an aligned position under the probe card and raises the wafer until proper contacts are established between the probes and DUT's input/output (I/O) pads.
Membrane probe technology has also been developed by forming an array of microcontacts, generally known as contact bumps, on a thin and flexible dielectric film, i.e., a membrane. For each contact bump, a microstrip transmission line is formed on the membrane for electric connection to the performance board. The contact bumps are formed by a metal plating method. The microstrips are formed by use of the photolithographic methods. Because the contact bumps can be formed right on the membrane, unlike the conventional probes, membrane probes have no extending needles or blades to hold the fine probe tips in place. The contact bumps can be formed to create a large number of contacts with high probe density. Additionally, improvements in mechanical and electric performance are realized by the membrane probes because of the simplicity of its configurations.
One critical prerequisite for successful IC test by either the membrane or conventional probe cards is to establish proper electrical contact between the probes and the DUT's input/output pads. In practical testing operations, the probe card and its probe tips or the contact bumps may not be exactly coplanar with the surface of the DUT's I/O pads. In the case of membrane probe cards, a self-leveling system (U.S. Pat. No. 4,906,920) is used to accommodate this non-coplanarity condition. To compensate for the same such variations with conventional probe cards, the wafer dispensing system is controlled to raise the wafer a predetermined distance beyond the first point of contact to assure proper contact with all probes. Such practice is generally referred to as overdrive.
Another factor which may affect the testing operation is the nonconductive oxide film which typically forms on the surface of the I/O pads of a DUT. This thin layer is only five to ten nanometers in depth but due to its high degree of resistance the accuracy of current, voltage, or frequency response measurements is severely impaired. In the case of conventional probe cards the problem is resolved by holding the probes at a small angle with respect to the plane of the DUT. As the probes are pushed by the wafer, the probes slide along the surface of the pads. This horizontal movement creates a scrubbing action which removes the oxide film on the surface. For the membrane probe, a scrubbing motion is created by using a set of flexure pivot assemblies. As disclosed in U.S. Pat. No. 4,918,383 entitled "Membrane Probe with Automatic Contact Scrub Action" by Huff et al. (Apr. 17, 1990).
The probes and the membrane with its contact bumps are therefore subjected to the forces of vertical `overdrive` and horizontal `pulling` and `scrubbing` in the test operations. These stressful operation conditions can cause the membrane to lose resiliency. Material deteriorations and structure break down can also occur which cause premature damages of the probe card.
U.S. Pat. No. 4,906,920, entitled "Self-leveling Membrane Probe" (issued on May 6, 1990), Huff et al. discloses a self-leveling mechanism to improve the surface coplanar alignment between a membrane probe contact bumps and a DUT. Pivotal pins, together with leaf springs and the translation stages, provide a small angular rotational freedom for surface alignment adjustments. In addition, an elastomeric bed is placed between the self-leveling mechanism and the membrane and its contact bumps to cushion the force of the probe on the DUT.
The self-leveling mechanism and the elastomeric bed are useful in reducing the stress placed upon the contact bumps. However, when exposed to excessive temperature in hot chip testing in combination with excessively high loading forces, all elastomers exhibit a phenomenon known as compression set or creep. This can lead to premature damage of the contact bumps and their transmission lines. The elastomeric layer must be protected in order to prevent such premature damages.
Additionally, the membrane along with the elastomer bed is subject to lateral forces while making the horizontal scrubbing motion to remove the oxide film from the DUT's I/O pads during testing. Excessive overdrive (force) and temperature will result in making these lateral forces unacceptable and can impaire the effectiveness of the scrubbing motion. The elastomer layer must be protected in order to prevent loss of mechanical coupling through friction, between the elastomer and the membrane.